Japan: Toshiba Electronic Devices & Storage Corporation has developed a new design technology for trench-gate silicon carbide (SiC) MOSFETs that reduces power losses while improving short-circuit durability.
The approach optimises the bottom p-well structure formed beneath the trench and refines the junction field-effect transistor (JFET) region, including its width and doping levels.
Toshiba says the new structure reduces short-circuit energy generated inside the device and limits temperature rise, resulting in improved reliability while maintaining gate oxide stability. The company also highlights lower on-resistance, supporting higher energy efficiency in power conversion systems.
Power semiconductors are essential for efficient electricity control and conversion and play a key role in achieving energy savings and carbon neutrality. SiC MOSFETs are widely seen as next-generation devices, offering higher efficiency than traditional silicon MOSFETs and are increasingly used in electric vehicles, renewable energy systems, and data centre power supplies.
In trench-gate SiC MOSFETs, protective electric-field structures are used to ensure gate oxide reliability. However, the JFET region can affect current flow and thermal behaviour, making it challenging to balance low resistance with strong short-circuit performance.
Toshiba addressed this by introducing a bottom p-well design under the trench and adjusting JFET width and doping concentration. Prototype devices showed around a 25 % reduction in on-resistance compared with conventional designs, while maintaining short-circuit robustness.
The company has confirmed that device degradation is linked to short-circuit energy, and that reducing this energy improves reliability. Test samples of the 1200 V device “TW007D120E” have already begun shipping.
Toshiba will present the technology at ISPSD 2026 in Las Vegas, supported by research under Japan’s NEDO programme.
Source: Toshiba
